International Workshop on Smart Networks, Data Processing and Infrastructure Units

May 25, 2023

Hamburg, Germany

Held in conjunction with:

Hamburg, Germany

In recent years, the use of smart network adapters, also known as SmartNICs, has seen a rapid increase. These adapters offer new capabilities for high-performance computing (HPC) beyond standard packet processing. Examples include data processing units (DPUs) or infrastructure processing units (IPUs) that have evolved into system-on-a-chip’s (SoCs) that can include programmable FPGAs, lightweight processing cores and specialized accelerators. DPUs are primarily used for data center operations such as packet filtering, I/O acceleration and security, but there is also growing interest in using them to accelerate HPC applications by offloading communication, I/O management and even part of the application computational workload to them.

This workshop brings together experts from the HPC community, including representatives from national laboratories, HPC vendors and international research centers, to share their knowledge and insights on how DPUs can be leveraged to accelerate HPC applications. In addition to presentations on current research and developments, participants will also discuss new trends in DPU design and their potential use cases. Presenters include researchers, tools developers and HPC users, with a keynote speaker to provide an overview of the evolution of SmartNICs and why they are becoming increasingly important in today’s computing landscape.


The workshop topics will include but not be limited to the following:

  • Application use-cases for Data Processing Units

  • Programming Interfaces

  • Tools that leverage Data Processing Units

  • Storage infrastructure opportunities

  • Latest DPUs from multiple vendors

  • HPC Users, Programmers, Practitioners interested in sharing their experience with DPUs

Workshop Organizers

Rich Graham


Philip Roth


Dirk Pleiter


Oscar Hernandez


Estela Suarez


Program Committee Members

Gilad Shainer


Jeff Young

Georgia Tech

Nick Malaya


Tom Papatheodore


Steve Poole


Filippo Spiga


09:00-9:3030 minWelcome and Invited Talk: Smart Networks in HPC An Architecture Perspective Challenges and OpportunitiesMartin Schulz, Technical University of MunichTalk
DPU Efforts Around the World (Vendors)
09:30-10:0030 minA Deep Dive into DPU Computing – Addressing HPC/AI Performance BottlenecksGilad Shainer, NVIDIATalk
10:00-10:3030 minGetting data where it’s needed – potential for CPU, GPU, accelerators, and smart networksSam Antao, AMDTalk
Efforts Around the World (Use-cases)
10:30-11:0030 minIntelligent algorithms on intelligent networks—experiences and challenges using NVIDIA’s BlueField technologyTobias Weinzierl, Durham University / TUMTalk
11:00- 11:30Coffee Break
11:30-12:0030 minPrinciples and practice of algorithm design on DPU systemsRich Vuduc,
Georgia Institute of Technology
12:00-12:3030 minCo-Design with DPUsRyan Grant,
Queen’s University
12:30-13:0030 minsPIN: in-network high-performance low-power packet processingTimo Schneider, ETHZTalk
13:00Closing Remarks / Adjourn